The present invention is directed to programmable controllers typically used for control of industrial machines and processes which, since approximately 1969 when they were first developed, have been utilized to replace relay ladder-type logic previously used to achieve such control functions. U.S. Pat. No. 3,686,639, Fletcher et al, 3,994,984, Morley et al, 3,930,233, Morley et al, and U.S. patent application Ser. No. 895,581 filed Apr. 12, 1978 and assigned to the present assignee, illustrate the historical development of the programmable controller art. It is known that other patents have been issued to other companies manufacturing programmable controllers, including Allen-Bradley Co., Texas Instruments, and General Electric.
The present invention is an improvement over these prior art programmable controllers. It provides a dual data base capability with a unique data packing scheme while presenting a uniform word size to the external world and a user control hardware network logic solver utilizing a programmable logic array that allows the user to specify various node elements, including horizontal and vertical shorts. The processor hardware and software include a FIFO system to improve the memory throughput by taking advantage of the fact that the programmable controller solves network nodes in a sequential fashion. Two ports are provided to the memory including a random access port and the FIFO port. These features and a memory management system in which up to one-half million words can be directly addressed by a page register have not been previously utilized in the programmable controller art. Furthermore, the present invention performs input/output (I/O) logically throughout the scan solving the user networks rather than performing the I/O at a particular location in memory. Furthermore, a multi-phase clock system is utilize in the bus design to increase overall system speed.
These improvements yield a faster, more powerful and cost effective programmable controller than prior art controllers.